With an increase in performance of information processing equipment, such as apparatuses and servers for communication core systems, it has been become desirable that the information processing speed of electronic apparatuses and semiconductor devices mounted in the electronic apparatuses be improved. To improve the information processing speed of semiconductor devices or the like, it is desirable that the transmission data bandwidth be made larger, and that the number of bits transmitted per unit time be increased. For example, it is desirable that a high data rate, such as 25 Gbps or 50 Gbps, be stably achieved.
The related art is disclosed in Mansuri, M, et al., “Methodology for on-chip adaptive jitter minimization in phase-locked loops,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 11, pp. 870, 878, November 2003; Joon-Yeong Lee, et al., “A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 8, pp. 2466, 2472, August 2014; Hyung-Joon Jeon, et al., “A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy,” IEEE Journal of Solid-State Circuits, vol. 48, no. 6, pp. 1398, 1415, June 2013; and Sungchun Jang, et al., “An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection,” IEEE Transactions on Circuits and Systems II. 